1. Field of the Invention
This invention relates to multilayer ceramic substrates designed to improve the mechanical and electrical reliability of surface mounted features. More particularly, the invention relates to ceramic substrates having a plurality of vias conductively connected by metal straps, having certain vias directionally located nearest to the center of the substrate, and the metal straps pointing in a predetermined location towards the substrate center, and methods for making the same.
2. Description of Related Art
As semiconductor technology moves towards increasingly higher speeds and higher reliability, high performance ceramic packaging becomes a requisite necessity to integrated circuit design. Within the high frequency, high performance electronic packages, electrical leakages are amplified by the parallel paths of multiple conductive vias within the multiple layers of the final substrate. Interconnection between buried conductor levels within a layered substrate is usually achieved through a plurality of vias, which are formed prior to the lamination of the multiple layers. Ideally, fewer vias would reduce the unwanted parasitic capacitances and resultant leakages. In the design limit, only one via is optimally desired in a single layer in order to eliminate the parallel path leakages and maintain high frequency electrical performance requirements when connecting signal features between the multiple layers. Left unchecked, the parasitic capacitance would dominate the high frequency performance characteristics of the substrate. Thus, a layer having a single via, if functionally and reliably achievable, would enhance the operational reliability of a high frequency signal net.
The reliability of the electrical connections between the ceramic substrate and a printed circuit board is generally affected by a number of parameters, which include the difference in the coefficient of thermal expansion (CTE) between the substrate and the board, the comparative stiffness between the substrate and the board, the size of the solder array, and height of the solder joint, to name a few. The board and substrate expand and contract during thermal cycling, causing strain in the solder connections between the two, with the greatest strain occurring at the outermost connections relative to the center of the solder array. In this manner, repetitive thermal cycling will eventually fatigue the solder connections to failure, creating openings or discontinuities in the electrical pathways between the ceramic substrate and the board. A layered substrate design that is capable of reducing this strain would ultimately enhance the life and reliability of the substrate.
Typically, a multilayer ceramic substrate is manufactured by the following conventional method. First, a plurality of holes is formed through a green sheet of glass-ceramics, and these holes are filled with copper paste to form a plurality of vias. Then, copper paste is screen-printed on the green sheet to form a plurality of thick film pads connected to the vias, and a plurality of thick film patterns are connected to the thick film pads. The green sheet is then dried. A number of green sheets are prepared in this manner, and laminated and bonded together through the application of heat and pressure. The bonded green sheets are then sintered to manufacture a multiple layered ceramic substrate.
When electrical performance requirements are not as rigid, several redundant vias can be used to connect the I/O pad to an internal anchor pad. Generally, the multiple vias are arranged so as to allow as many vias as will fit within the area of a subsequent surface feature, such as the I/O pad. In order to provide and ensure electrical continuity, however, each via from a first layer is aligned with a corresponding via from a second layer. An exception to this can be found in U.S. Pat. No. 5,549,778 issued to Yokoyama, et al., on Aug. 27, 1996, entitled “MANUFACTURING METHOD FOR MULTILAYER CERAMIC SUBSTRATE.” In Yokoyama, “dummy” vias are taught to help anchor the surface feature (pad) to the underlying ceramic. These dummy vias are nonfunctioning and merely serve to mechanically assist in the anchoring of the surface feature. The dummy vias provide no electrical continuity with vias in the underlying layers.
Multiple, redundant vias can be detrimental in high frequency, high performance packages. Parasitic losses are increased at higher frequencies, with the losses amplified by the number of parallel via paths introduced in each layer. Additionally, in an anchored pad configuration, an original via structure places the interconnection via in alignment with the signal via at the next layer in the package. This often results in the via being located at the outermost or center location on the I/O pad, which is the higher stress location, at a higher local distance-to-neutral point (DNP), and becomes an early failure location as the via is stressed under tensile and shear during machine thermal cycling. Vias under these conditions become fatigued and fractured. The further the via is located away from the substrate center, the more stress and strain it will undergo.
In U.S. Pat. No. 6,312,791 issued to Fasano, et al., on Nov. 6, 2001, entitled “MULTILAYER CERAMIC SUBSTRATE WITH ANCHORED PAD,” multiple vias are anchored to a surface pad of the first, bottom layer, with at least one of the anchored vias in electrical contact with vias in other layers above. Specifically, Fasano teaches having the outer pad attached to the multilayer ceramic substrate, which is anchored to a middle pad of the substrate by a plurality of vias, which in turn are anchored to an inner pad of the substrate by a second plurality of vias. In each instance, a thick film contact pad is utilized to form electrical continuity among vias. Additionally, multiple vias are constructed in the innermost layers, connected to I/O pads. Outer layers are shown with a single via electrically connected to a single via in a layer below. Importantly, no attempt is made to reduce the tensile and shear stresses on the vias by placing them closer to the substrate center.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a multilayered ceramic substrate with a plurality of vias, having improved high frequency reliability and high electrical performance.
It is another object of the present invention to provide a multilayered ceramic substrate with a plurality of vias, having a standard via grid, that under high frequency applications does not increase parasitic capacitance or electrical leakage.
A further object of the invention is to provide a multilayered ceramic substrate with a plurality of vias that eliminates early failures on high local distance-to-neutral point vias.
It is yet another object of the present invention to provide a multilayered ceramic substrate with a plurality of vias that allows for increased application space for the electronic package.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.